This invention relates generally to insulated gate field effect transistors (IGFET) such as the metal oxide silicon (MOS) transistor, and more particularly the invention relates to a lateral IGFET and MOS (LDMOS) transistor having a reduced layout area and pitch and reduced grounded source resistance and capacitance in power applications.
The laterally diffused MOS transistor is used in power-applications for low-side switches as well as for RF/microwave power amplifiers. The devices are typically fabricated in an epitaxial silicon layer (P-) on a more highly doped silicon substrate (P+). A grounded source configuration is achieved by deep P+ sinker diffusion from the source region to the P+ substrate, which is grounded.
However, the diffused sinker has a lateral diffusion which increases the necessary width of the source contact. Further, the deep P+ sinker must be kept away from the gate and channel regions in order to achieve a controlled threshold voltage. For example, in an epitaxial layer having 5 .mu.m thickness, the P+ sinker must be greater than 5 .mu.m in depth and will have greater than 4 .mu.m lateral diffusion on all sides. For a 2 .mu.m minimum pattern size, the pitch of a two transistor cell having a common source or drain is on the order of 30 .mu.m. Further, the heat budget for a diffused sinker causes dopant out diffusion from the heavily doped substrate, which increases parasitic capacitance of the device.
The present invention is directed to a process and resulting LDMOS structure having reduced pitch, source resistance, and capacitance.